Measuring internal signals of an integrated circuit
US10459030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Oct 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either directly or via the buffer to the first external pin of the IC in order to calibrate the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.