Memory device, and data processing method based on multi-layer RRAM crossbar array
US10459724B2 · kind B2 · utility
14Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jul 17, 2018 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Jul 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.