Ceramic module for power semiconductor integrated packaging and preparation method thereof
US10461016B2 · kind B2 · utility
1Cited by
2References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 9, 2018 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Jul 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A ceramic module for power semiconductor integrated packaging and a preparation method thereof are disclosed. The ceramic module includes a ceramic substrate and an integrated metal dam layer. By providing the integral metal dam layer on the upper surface of the ceramic substrate and forming cavities around die bonding regions, the semiconductor chip can be hermetically sealed. By providing a heat dissipation layer on the lower surface of the ceramic substrate, the heat generated by the semiconductor chip can be quickly conducted to the outside. The product has a simple production process and high product consistency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.