Semiconductor memory device and method of manufacturing the same
US10461153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2018 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Feb 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.