Flat gate commutated thyristor
US10461157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2018 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Mar 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
Abstract
The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells, each thyristor cell comprising a cathode region; a base layer; a drift layer; an anode layer; a gate electrode which is arranged lateral to the cathode region in contact with the base layer; a cathode electrode; and an anode electrode. Interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar. In addition, the base layer includes a gate well region extending from its contact with the gate electrode to a depth, which is at least half of the depth of the cathode region, wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 μm from the cathode region. The base layer includes a compensated region of the second conductivity type, the compensated region being arranged …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.