Adaptive multi-level gate driver
US10461730B1 · kind B1 · utility
16Cited by
1References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2018 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Sep 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate driver circuit for driving a power switch includes a gate driver having a first input for receiving an input signal and an output coupled to the power switch, the gate driver providing a primary gate current and an auxiliary gate current, and a differential voltage sensor having a first input for receiving the input signal, a second input coupled to a power supply voltage, a third input coupled to a terminal of the power switch, and an output coupled to a second input of the gate driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.