Reference-less frequency detector with high jitter tolerance
US10461757B2 · kind B2 · utility
0Cited by
10References
22Claims
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Key dates
| Filing date | Dec 29, 2016 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.