Successive approximation register analog-to-digital converter chopping
US10461762B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2018 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Aug 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.