Digital-to-analog converter (DAC) design with reduced settling time
US10461768B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2018 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Dec 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure provide a digital-to-analog converter (DAC). The DAC generally includes a plurality of transistors selectively coupled to an output of the DAC, and a biasing circuit coupled to gates of the plurality of transistors. The biasing circuit may include a first transistor having a gate coupled to a drain of the first transistor, a first buffer having an input coupled to the gate of the first transistor, a second transistor having a gate coupled to an output of the first buffer, a first resistive-capacitive (RC) circuit having a first resistive element and a first capacitive element, the first RC circuit being coupled between the gate of the first transistor and the gate of the second transistor, and a first switch coupled between the first resistive element and the first capacitive element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.