Method using logical based addressing for latency reduction
US10466911B2 · kind B2 · utility
1Cited by
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25Claims
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Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Feb 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.