Method for maximizing frequency while checking data integrity on a physical interface bus
US10466920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Aug 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K2207/1018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.