Thread pause processors, methods, systems, and instructions
US10467011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2014 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Apr 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.