Technologies for memory margin aware reliable software execution
US10467028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Jan 16, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4843
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for reliable software execution include a computing device having a memory that includes multiple ranks. The computing device trains the ranks of the memory and determines a consolidated memory score for each rank. Each consolidated memory score is indicative of a margin of the corresponding rank. The computing device identifies a higher-margin address range using the consolidated memory scores. The higher-margin memory address range is mapped to a higher-margin memory rank. The computing device loads high-priority software into the higher-margin memory address range. The high-priority software may include an operating system or a critical application. A pre-boot firmware environment may publish the consolidated memory scores to a higher-level software component, such as the operating system. The pre-boot firmware environment may map a predetermined address range to the higher-margin memory rank. A critical application may request to be loaded into a higher-margin address range. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.