Shift register unit, driving method thereof, gate driving circuit and display device
US10467937B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 10, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | May 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure discloses a shift register unit, a driving method thereof, a gate driving circuit and a display device. The shift register unit comprises an input circuit, a reset circuit, a control circuit, a pull-down circuit and an output circuit, a first control terminal of the output circuit is coupled to a first node, its first input terminal is coupled to a second clock signal terminal, its first output terminal is coupled to a signal output terminal, both terminals of the pull-down circuit are coupled to a first clock signal terminal and the first node, respectively, and the pull-down circuit may pull down the potential of the first node via the first clock signal terminal, which may thus avoid that the potential of the first node also rises when the potential of the second clock signal terminal rises, and the signal of the second clock signal terminal is mistakenly provided to the signal output terminal to cause various poor display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.