Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communication
US10468078B2 · kind B2 · utility
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326References
16Claims
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Key dates
| Filing date | Mar 24, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Dec 18, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.