DRAM row sparing
US10468118B2 · kind B2 · utility
4Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2014 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Jul 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2229/763
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.