Semiconductor memory device
US10468350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Oct 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.