Integrated enhancement mode and depletion mode device structure and method of making the same
US10468406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2014 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | May 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.