Semiconductor memory devices
US10468414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2018 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Aug 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory devices are provided. A semiconductor memory device includes a substrate and a stack including a plurality of layers on the substrate. Each of the plurality of layers includes semiconductor patterns and a first conductive line that is connected to at least one of the semiconductor patterns. A second conductive line and a third conductive line penetrate the stack. The semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern that are adjacent and spaced apart from each other in a first layer among the plurality of layers. The third conductive line is between, and connected in common to, the first and second semiconductor patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.