Variable delay
US10469091B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Feb 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/189
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This disclosure describes controlling a variable delay system with a control signal generated in a phase-locked loop (PLL). Furthermore, aspects describe generating a compensation current based on a number of edges of pulses propagating through a variable delay line including multiple delay elements. The number of edges propagating through the variable delay is determined by computing a difference between a number of edges entering the variable delay line and a number of edges exiting the variable delay line. The compensation current is derived from a mirrored version of the current of the control signal of the PLL. Thus, the techniques and systems in this disclosure provide accurate and repeatable control of a variable delay line over variations in temperature and process using low-power circuits. Furthermore, the input signal to the variable delay line may be asynchronous with respect to a system clock or a reference signal of the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.