Successive approximation register analog-to-digital converter, electronic device and method therefor
US10469095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2018 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460). The DAC (430) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller (418) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC (430) and the digital signal reconstruction circuit (450) to implement a small signal mapping mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.