Patent · US Active

Successive approximation register (SAR) analog to digital converter (ADC) with partial loop-unrolling

US10469096B1 · kind B1 · utility

2Cited by

1References

14Claims

0Family size

Assignee

eSilicon Corporation · US

Inventors

Nicola Ghittori · Pavia, IT
Claudio Nani · Milano, IT
Enrico Monaco · Carpi, IT

Key dates

Filing date	Jan 3, 2019
Grant date	Nov 5, 2019
Priority date	—
Expiry date	Jan 3, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH03M1/365
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.