Anti-interference semiconductor device for optical transceiver
US10469174B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2019 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Mar 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is an anti-interference semiconductor device for an optical transceiver. The semiconductor device includes: a back metallization layer, a p++ bearing wafer layer, a P-type epitaxial layer, an isolation layer and a metal layer arranged from bottom to top. The back metallization layer serves as a substrate, on which the p++ bearing wafer layer is formed. The P-type epitaxial layer is formed on the p++ bearing wafer layer. The metal layer is formed on the isolation layer. The semiconductor device includes at least two N-type heavily doped grooves, two P-type heavily doped grooves and a plurality of deep through-silicon vias, which are formed in the P-type epitaxial layer and the isolation layer. The deep through-silicon vias are distributed and divided into at least two rows. The N-type heavily doped grooves and the P-type heavily doped grooves are alternately arranged at two sides of the deep through-silicon vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.