Minimum latency link layer metaframing and error correction
US10469200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2018 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Feb 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing latency associated with metaframe error correction. Embodiments receive, via a first port of a plurality of ports, a stream of bits within a metaframe. Upon evaluating a first cyclic redundancy check (CRC) for a first portion of the stream of bits and determining that the first CRC is valid, a measure of latency incurred in transmitting the first portion is reduced, relative to first performing forward error correction (FEC) decoding for the first portion prior to transmission, by transmitting the first portion of the stream of bits without performing FEC decoding for the first portion of the stream of bits. Upon evaluating a second CRC for a second portion of the stream of bits and determining that the second CRC is invalid, FEC decoding is performed for the second portion of the stream of bits before forwarding the second portion of the stream of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.