Clock recovery circuit and method of operating same
US10469214B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2018 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Dec 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Techniques and mechanisms for a clock recovery circuit to generate a cyclical signal based on data signals which are susceptible to circuit switching jitter. In an embodiment, a clock recovery circuit comprises switch circuitry which receives a first signal representing a logical combination of multiple pulsed signals (which, in turn, are each based on a different respective differential data signal). The switch circuitry provides to latch circuitry of the clock recovery circuit a second signal based on the first signal. The latch circuitry generates a cyclical signal based on the second signal, and transitions the switch circuitry between an open-circuit state and a closed-circuit state. In another embodiment, the latch circuitry implements a predetermined and configurable time period between a transition of the cyclical signal and a next subsequent logic state transition of the cyclical signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.