Mulit-lane synchronous reset for coherent receivers
US10469242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2018 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Oct 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.