Patent · US Active

Low-latency pipeline for media-to-ethernet frame packaging

US10469633B2 · kind B2 · utility

0Cited by

7References

14Claims

0Family size

Assignee

Marvell World Trade Ltd. · BB

Inventors

Thomas Kniplitsch · Insheim, DE
Manfred Kunz · Berlin, DE
Lukas Reinbold · Hollfeld, DE

Key dates

Filing date	May 8, 2018
Grant date	Nov 5, 2019
Priority date	—
Expiry date	May 8, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH04N21/43632
WIPO fieldAudio-visual technology
WIPO sectorElectrical engineering

Abstract

A conversion pipeline includes a media input stage, a packetizer, a MAC engine and a PHY interface. The media input stage is configured to receive from a media source a sequence of media frames carrying media content. The packetizer is configured to convert the media frames into a sequence of Ethernet packets by generating headers and appending portions of media frames to corresponding generated headers, including appending a first portion of a first media frame to a first generated header before the first media frame is fully received. The MAC engine is configured to commence outputting a first Ethernet packet as an uninterrupted unit, the first Ethernet packet including the first header and payload bits corresponding to the first portion of the first media frame, before the first media frame is fully received. The PHY interface is configured to transmit the Ethernet packets over a network.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.