Redundancy coding stripe based on coordinated internal address scheme across multiple devices
US10474528B2 · kind B2 · utility
5Cited by
9References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2017 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Jan 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method pertains to operating non-volatile memory systems. Technology disclosed herein efficiently uses memory available in non-volatile storage devices in a non-volatile memory system. In some aspects, non-volatile storage devices enforce a redundancy coding stripe across the non-volatile storage devices formed from chunks of data having internal addresses assigned in a coordinated scheme across the storage devices. In some aspects, non-volatile storage devices enforce a redundancy coding stripe across the non-volatile storage devices at the same internal addresses in the respective non-volatile storage devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.