Debug data saving in host memory on PCIE solid state drive
US10474618B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 4, 2014 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Jul 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0751
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and system are provided for implementing debug data saving in host memory on a Peripheral Component Interconnect Express (PCIE) solid state drive (SSD). Upon Power Loss Interruption (PLI) event detected in a solid state drive (SSD), the SSD transfers debug data directly to the host system main (DRAM) memory via a Peripheral Component Interconnect Express (PCIE) bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.