Semiconductor package
US10475749B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 2018 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | May 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor chip on a first substrate, a first mold layer provided on the first substrate to cover a side surface of the first semiconductor chip, a solder structure provided on the first substrate, and a second substrate provided on the solder structure. A guide receptacle is formed at one of a top surface of the first mold layer and a bottom surface of the second substrate, a first alignment protrusion is formed at the other of the top surface of the first mold layer and the bottom surface of the second substrate, and at least a portion of the first alignment protrusion is provided in the guide receptacle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.