Three-dimensional vertical NOR flash thin-film transistor strings
US10475812B2 · kind B2 · utility
61Cited by
1References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2019 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Jun 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.