Reliable non-volatile memory device
US10475891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2016 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Jan 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region having a pair of non-volatile memory cells with a split gate. A split gate includes first and second gates. The first gate is an access gate and the second gate is a storage gate with a control gate over a floating gate. A common second S/D region is disposed adjacent to second gates of the first and second memory cells and first S/D regions are disposed adjacent to the first gates of the first and second memory cells. An erase gate is disposed over the common second S/D region. The erase gate is isolated by the second S/D and second gates by dielectric layers. A silicide block is disposed over the memory cell pair, covering the erase gate at least portions of the second gates of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.