Encoding device, memory controller, communication system, and encoding method
US10481971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2016 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Jun 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell.A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.