Memory controller architecture with improved memory scheduling efficiency
US10482934B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Jan 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.