Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory
US10482935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | May 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.