Embedded memory in back-end-of-line low-k dielectric
US10483121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | May 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.