Semiconductor device including memory cell array with transistors disposed in different active regions
US10483268B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Sep 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.