Array substrate, manufacturing method thereof and display device
US10483294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2015 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Sep 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
Abstract
An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises a gate electrode layer, an active layer and a source-drain electrode layer that are disposed on a substrate. The substrate comprises a storage capacitance region thereon II. In the storage capacitance region II, projections of the gate electrode layer and the active layer on the substrate are at least partially overlapped, and projections of the active layer and the source-drain electrode layer on the substrate are at least partially overlapped. The array substrate can effectively increase the storage capacitance without increasing an area occupied by the storage capacitance region, which is advantageously to reduce a pixel area and increase PPI.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.