Method of fabricating a power semiconductor device
US10483359B2 · kind B2 · utility
0Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2017 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Nov 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.