Level shifter
US10483977B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2019 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, and a low state pulse generator. The high voltage latch circuit includes a non-inverting output terminal, an inverting output terminal, a high state trigger input terminal, and a low state trigger input terminal. The low voltage latch circuit includes a high state trigger input terminal and a low state trigger input terminal. The high state trigger input terminal is coupled to the inverting output terminal of the high voltage latch circuit. The low state trigger input terminal is coupled to the non-inverting output terminal of the high voltage latch circuit. The high state pulse generator is coupled to the high state trigger input terminal of the high voltage latch circuit. The low state pulse generator is coupled to the low state trigger input terminal of the high voltage latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.