Calibration of radix errors using Least-Significant-Bit (LSB) averaging in a Successive-Approximation Register Analog-Digital Converter (SAR-ADC) during a fully self-calibrating routine
US10483995B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2019 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Feb 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-calibrating Analog-to-Digital Converter (ADC) performs radix error calibration using a Successive-Approximation Register (SAR) to drive test voltages onto lower-significant capacitors. The final SAR code is corrected by performing LSB averaging on LSB averaging capacitors and then accumulated, and the measurement repeated many times to obtain a digital average measurement. An ideal radix or ratio of the measured capacitor's capacitance to a unit capacitance of an LSB capacitor is subtracted from the digital average measurement to obtain a measured error that is stored in a Look-Up Table (LUT) with the ideal radix. Radix error calibration is repeated for other capacitors to populate the LUT. During normal ADC conversion, the SAR code obtained from converting the analog input is applied to addresses the LUT, and all ideal radixes and measured errors for 1 bits in the SAR code are added together to generate an error-corrected digital value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.