Glitch free phase selection multiplexer enabling fractional feedback ratios in phase locked loops
US10484027B2 · kind B2 · utility
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5References
30Claims
0Family size
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Key dates
| Filing date | Jan 30, 2017 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | May 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In some aspects, a method for phase multiplexing includes receiving a plurality of phases, selecting one of the plurality of phases based on a select signal using a multiplexer, and outputting the selected one of the plurality of phases at an output of the multiplexer. The method also includes gating the output of the multiplexer during a glitch at the output of the multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.