Multilayer bus board
US10485092B2 · kind B2 · utility
3Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2016 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Feb 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/2018
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multilayer bus board comprising a multilayer stacked assembly including a plurality of electrically conductive first layers, and at least one second dielectric layer disposed between adjacent first layers; and a frame formed of a dielectric material, the frame encapsulating at least a portion of the multilayer stacked assembly and mechanically maintaining the first and second layers in secure aligned abutting relation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.