Shift read command for performing rank-to-rank transfers in semiconductor memory devices
US10489061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2018 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | May 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first rank includes a plurality of first semiconductor memory devices, and a second rank includes a plurality of second semiconductor memory devices. The command/address signal lines are shared by a controller, the first rank, and the second rank, and the data lines are shared by the controller, the first rank, and the second rank. When performing a data movement operation of moving data between the first rank and the second rank, the controller applies a shift read command to one of the first rank and the second rank through the command/address signal lines and applies a normal write command or a shift write command to another of the first rank and the second rank through the command/address signal lines after a time corresponding to a value obtained by subtracting the value of the write latency from the value of the read latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.