Programmable integrated circuits with multiplexer and register pipelining circuitry
US10489116B1 · kind B1 · utility
10Cited by
6References
13Claims
0Family size
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Inventor
Key dates
| Filing date | Jul 9, 2014 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Feb 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement amongst others multiplication, addition, sum-of-product, and multiply-accumulation operations in a first mode. In a second mode, the specialized processing blocks may operate as multiplexers and several specialized processing blocks may be cascaded to implement wider multiplexing functions. In a third mode, the specialized processing blocks may operate as register pipelines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.