Scheduling of concurrent block based data processing tasks on a hardware thread scheduler
US10489206B2 · kind B2 · utility
3Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Feb 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node is configured to execute a task, and a hardware thread scheduler coupled to the plurality of hardware data processing nodes, the hardware thread scheduler configurable to concurrently execute a first thread of tasks and a second thread of tasks on the plurality of hardware data processing nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.