Flushing data content in response to a power loss event to a processor
US10489237B2 · kind B2 · utility
0Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2014 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Jul 29, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example, a processor may include a processor core with a central processing unit as well as a processor cache separate from the processor core. The processor may also include flushing circuitry. The flushing circuitry may identify a power loss event for the processor. In response, the flushing circuitry may selectively power the processor by providing power to the processor cache but not to the processor core. The flushing circuitry may further flush data content of the processor cache to a non-volatile memory separate from the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.