Apparatus and method to improve performance in DMA transfer of data
US10489322B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2019 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Mar 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a first memory and a direct memory access (DMA) controller. The DMA controller includes a second memory to store the received packet and a third memory, and receives a packet including a header where information for DMA is registered and data to be stored in the first memory. The DMA controller acquires and stores, in the third memory, the header and a beginning portion of a given length from beginning of the data of the packet stored in the second memory. The DMA controller reads the data included in the packet from the third memory when it is determined, based on the header, that a data length of the data included in the packet is less than or equal to the given length, and performs storage of the read data by DMA in the first memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.