TFT circuit and shift register circuit
US10490144B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2017 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Jun 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A TFT circuit (101) includes a first node (N1) to which a first low potential (Vc) is supplied, a depression-type first TFT (21) which is arranged between the first node (N1) and low-potential wiring (11) for supplying a second low potential (Va) higher than the first low potential (Vc), and in which a drain terminal is connected to the first node, and a depression-type second TFT (22) which is arranged between the first TFT (21) and the low potential wiring (11) and in which a source terminal is connected to a source terminal of the first TFT, in which the first low potential (Vc) is supplied to a gate terminal of the second TFT, a second node (N2) enterable a floating state is formed between the source terminal of the first TFT and the source terminal of the second TFT, and the second node (N2) is connected to a sub-circuit (SC1) which is settable a potential of the second node (N2) to be lower than the second low potential (Va) and higher than the first low potential (Vc).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.