Memory check ASIC for fuzes and safety and arming devices
US10490291B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2018 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldOther special machines
- WIPO sectorMechanical engineering
Abstract
A memory check ASIC for fuzes and safety and arming (S&A) devices. The memory check ASIC may comprise: an ASIC, data line, clock line, shutdown line, and reset line. The ASIC may operatively couple to a microcontroller having a flash-based memory and may comprise: a digital logic for verifying a calculated checksum based on contents of the flash-based memory. A clock signal along with the calculated checksum may be transmitted to the ASIC via the clock line and data line, respectively. A shutdown signal may be transmitted from the ASIC to the microcontroller via the shutdown line in response to the verification of the calculated checksum by the digital logic. A reset signal may synchronize sampling of the calculated checksum and may be latched by flip-flop circuits of the digital logic for a predetermined number of clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.